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N2012ZZ121T03 Datasheet
Irltefrupt requcsts can be gcneratcd hy cithcr chip or by ORing e:Lch together as a single intcrrupt pcr board. 'Ihe interrupt r.equests rre wired LO pins 9 and 11 0f the hiterrupt Cunnector on the top of ulc boucl. ALternateI-C the ifikfrupt reque'sts ccLn he jumper selected to diiTrre I.N'I'RQ', CNTRI.', or
N2012ZZ121T03 Price
Ultralow Quiescent Current Regulated Supply The LTC1754 contains an internal resistor divider (referto the Simplified Block Diagram) that typically draws l.5A from VOUT. During no-load conditions, this internal load causes a droop rate of only 150mV per second on VOUT with COUT =lOApplying a 2Hz t0 100Hz, 2% t0 5% duty cycle signal to the SHDN pin ensures that the circuit of Figure 2 comes out of shutdown frequently enough to maintain regulation. Since the LTC1754 spends nearly the entire time in shutdown, the no-load quiescent current is approximately (VOUT) (1.5cct\)/OIVIN).
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CHARACTERISTIC SYMBOL MIN TYP MAX UNIT
Clock Pulse Frequency f 1 20 MHz
Reset Pulse Frequency fRS 1 20 MHz
Cdl 200 pF
Clock Capacitance (Note 10) Cd2 200
Final Stage Clock Capacitance CdB 10 20 pF
Shift Gate Capacitance CSH 30 pF
Reset Gate Capacitance CRS 10 20 pF
Clamp Gate Capacitance CCP 10 20 pF


INVA INVB (Pins 4, 13): Inverting Input. ~ch of theINV pins is an inverting input of an op amp. Note that the INV pins are high impedance, sensitive nodes of the filter and very susceptible to coupling of unintended signals. Capacitance on the INV nodes will also affect the fre- quency response of thefilter sections. R)r these reasons, printed circuit connectionsto theINV pins must be kept as short as possible.