| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| N1951M | EPCOS | SIP-5 | 0427+ | 250 |
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| N1951M | EPCOS | ZIP-5 | 01+ | 只做原装，价格优 | 30 |
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| N1951M | S+M | SIP-5 | 190 |
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| N1951M | S+M | SIP-5 | 190 |
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N1951M Datasheet One of the most important aspects of the design is gen- eration of the REFCLK signal. This input provides the reference clock for the internal PLL which is multiplied by 10x or 20x to generate the baud rate clock.The ris- ing edge of REFCLK is continuously phase compared to the internal baud rate clock so that the PLL will speed up or slow down the VCO in order to keep these two signals aligned. It is therefore important that the REFCLK be as jitter-free as possible in order to mini- mize jitter introduced into the PLL and its baud rate clock. It is also desirable to have fast rising edges on this clock to minimize the time in which the signal tran- sitions from a LOW level to a HIGH level. A fast edge will reduce edge-detection ambiguity in the input buffer and therefore reduce jitter in the PLL. N1951M Price Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 0verflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 0perates as described above, but with the added feature that a l- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 0verflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 pulses.). N1951M on stock LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 0r 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 0r 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com M/A-COM's standard limiter series 2690 is a line of com- pletely passive solid state receiver protectors. They exhibit octave and multi-octave performance using a unique con- struction technique involving PIN diodes in broadband microstrip circuits. Careful diode selection allows a variety of device performance, trading off peak and average power handling, spike leakage and recovery time. Typical insertion loss and VSWR curves are shown below. |
