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N11402S10A5 Datasheet

Low Supply Current: 5000<A 0.2aA Supply Current in SHUTDOWN 500d\ Supply Current in RECEIVER ALIVE Mode ESD Protection Over +lOkV Operates from a Single 5V Supply Uses Small Capacitors: O.locF Operates t0 120k Baud Three-State Outputs Are High Impedance When Off Output Overvoltage Does Not Force Current Back into Supplies RS232 110 Lines Can Be Forced to +25V Without Damage Flowthrough Architecture
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Input and reference are transformer Isolated from each other and from DC power common. InsulatIon resistance from any AC input to output is greater than 200 megohms at 200 VDC. Separate analog and logIc grounds are supplied to mlnlmlze potentlal ground loop problems. The output is updated in l LSB steps whenever the Input angle changes. Error-free data can be tram ferred when "Converter Busy" Is at logic "0". Logic "1" Indicates that the output data Is changing ai that data should not be trdnsferred. Fan out Is 2 TTL loads. Before transferring data apply logic "0" to prevent output data from changing during transfer. The con verter will ignore an "Inhibit" command during the "Converter Busy" period. Fan in: 1 LPTTL.
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Collector-emitter breakdown voltage /C = 1 mA, /B = 0	V(BR)CEO	1 2			V
Collector-emitter cutoff current VCE = 20 V, VBE = 0	/CES			1 00	UA
Collector-base cutoff current VCB = 10 V, /E = 0	/CBO			1 00	nA
Emitter-base cutoff current VEB = 1 V, /C = 0	/EBO			1	UA
DC current gain /C = 30 mA, VCE = 8 V	hFE	50	1 00	200

2. Unless otherwise specified, a minimum clearance of .015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.). 3. Dimension "A" controls the overall package thickness. The maximum "A" dimension is the package height before being solder dipped. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. The index corner shall be clearly unique. 5. Dimension "B3" minimum and "L3" minimum and the appropriately derived castellation length define an unobstructed three dimensional space traversing all of the ceramic layers in which a castellation was designed. Dimension "B3" maximum and "L3" maximum define the maximum width and depth of the castellation at any point on its surface. Measurement of these dimensions may be made prior to solder dripping. 6. Chip carriers shall be constructed of a minimum of two ceramic layers

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