| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
N04G Datasheet
N04G Price Sequential Read (see Figure 13) The PCA9500 sequential read is an extension of either the current address read or random read. If the master doesn't issue a stop condition after it has received the eighth data bit, but instead issues an acknowledge, the PCA9500 will increment the address counter and use the next eight cycles to transmit the data from that location. The master can continue this process to read the contents of the entire memory. Upon reaching address 255 the counter will return to address o and continue transmitting data until a stop condition is received. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. N04G on stock viewed from the top of the package and the HV42 shifts in the clockwise direction. A data output bufferis provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the OE (Output Enable) or the STR (Strobe) inputs.
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