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The F100331 contains three D-type, edge-triggered master/slave flip-flops with true and complement outputs, a common clock (CPc) . and Master Set (MS) and Master Reset (MR) i_nputs. Each fli_p-flop has i_ndi_vi_dual clock (CPn) , Di_rect Set (SDn) and Di_rect Clear (CDn) Inputs. Data enters a master when both CPn and CPc are LOW and transfers to a slave when CPn or CPc (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50k ohm pull-down resistors.