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suppliers of MZ-141-K and PDF data of MZ-141-K

Part Numbert	Mfg	Packt	D/C	Descriptiont	Qty	Company/Contact
MZ-141-K	TAK		98+		4120	HK Green System Ltd Contact:hong123 Tel:86-755-0 Fax: Email: rena@hkgreen-system.com

MZ-141-K Datasheet

			- CC(DDR400@CL=3)		- C4(DDR400CL=3)
Parameter		Symbol	Min	Max	Min	Max	Unit	Note
Row cycle time		tRC	55		60		ns
Refresh row cycle time		tRFC	70		70		ns
Row active time		tRAS	40	70K	40	70K	ns
RAS to CAS delay		tRCD	15		18		ns
Row precharge time		tRP	15		18		ns
Row active to Row active delay		tRRD	10		10		ns
Write recovery time		tWR	15		15		ns
Internal write to read command delay		tWTR	2		2		tCK
	CL=3.0		5	10	5	10	ns
Clock cycle time	CL=2.5	tCK	6	12	6	12	ns	16
Clock high level width		tCH	0 45	0 55	0 45	0 55	tCK
Clock low level width		tCL	0 45	0 55	0 45	0.55	tCK
DQS-out access time from CK/CK		tDQSCK	-0.55	+0.55	-0.55	+0.55	ns
Output data access time from CK/CK		tAC	-0.65	+0.65	-0.65	+0.65	ns
Data strobe edge to ouput data edge		tDQSQ		0 4		0.4	ns	13
Read Preamble		tRPRE	0 9	1.1	0.9	1.1	tCK
Read Postamble		tRPST	0 4	0 6	0 4	0.6	tCK
CK to valid DQS-in		tDQSS	0.72	1.28	0.72	1.28	tCK
Write preamble setup time		tWPRES	0		0		ps	5
Write preamble		tWPRE	0.25		0 25		tCK
Write postamble		tWPST	0.4	0.6	0.4	0.6	tCK	4
DQS falling edge to CK rising-setup time		tDSS	0.2		0.2		tCK
DQS falling edge from CK rising-hold time		tDSH	0 2		0.2		tCK
DQS-in high level width		tDQSH	0.35		0 35		tCK
DQS-in low level width		tDQSL	0 35		0 35		tCK
Address and Control Input setup time		tIS	0 6		0 6		ns	h,710
Address and Control Input hold time		tIH	0.6		0.6		ns	h,710
Data-out high impedence time from CK/CK		tHZ		tAC max		tAC max	ns	3
Data-out low impedence time from CK/CK		tLZ	tAC min	tAC max	tAC min	tAC max	ns	3
Mode register set cycle time		tMRD	2		2		tCK
DQ & DM setup time to DQS, slew rate 0.5V/ns		tDS	0 4		0 4		ns	ij
DQ & DM hold time to DQS, slew rate 0.5V/ns		tDH	0.4		0 4		ns	ij
DQ & DM input pulse width		tDIPW	1 75		1 75		ns	9
Control & Address input pulse width for each input		tIPW	2 2		2 2		ns	9
Refresh interval time		tREFI		7.8		7.8	us	6
Output DQS valid window		tQH	tHP -tQHS		tHP -tQHS		ns	12
Clock half period		tHP	mi¨n tCH/tCL		mi¨n tCH/tCL		ns	11 12

MZ-141-K Price

Five different grades are available. The J and K grades are specified for operation over the OoC t0 700C temperature range. The A and B grades are specified from -400C to +850C, the T grade is specified from -550C to +1250C. The J and K grades are available in a 28-lead plastic DIP or 28-lead SOIC. All other grades are available in a 28-lead hermetically sealed ceramic DIP.
MZ-141-K on stock

Symbol	Parameter	Value	Unit
Vcc+	Supply Voltage - (note l)	18	V
Vid	Differential Input Voltage - (note 2)	±18	V
Vi	Input Voltage - (note 3)	18	V
VO	Output Voltage	18	V
lo	Output Current	20	mA
Toper	Operating Free-Air Temperature Range TS3702C TS37021 TS3702M	0 to +70 -40 to +125 -55 to +125	oC
Tstg	Storage Temperature Range	-65 to +150	oC

P	N
MAX6453 MAX6454	MAX6455 MAX6456	NAME	FUNCTION
1			Active-Low Push-Pull or Open-Drain Output. RESET changes from high to low when VCC or RSTIN drops below its selected reset threshold. RESET remains low for the 140ms (min) reset timeout period after all monitored power-supply inputs exceed their selected reset thresholds. MR does not affect RESET output. For open-drain outputs, connect to an external pullup resistor.
	1	RESET	Active-Low Push-Pull or Open-Drain Output. RESET changes from high to low when VCC or RSTIN drops below its selected reset threshold. RESET remains low for the 140ms (min) reset timeout period after all monitored power-supply inputs exceed their selected reset thresholds. RESET changes from high to low after MR input is held low for the 3.36s (typ) setup period and deasserts 140ms (min) after MR deasserts. For open-drain outputs, connect to an external pullup resistor.
2	2	GND	Ground
3	3	MROUT	Manual Reset Push-Pull or Open-Drain Output. MROUT asserts immediately after MR is pulled low. MROUT remains low for 140ms (min) after MR is deasserted. For open- drain outputs, connect to an external pullup resistor.
4	4	vcc	VCC Voltage Input. Power supply and input for the primary microprocessor voltage reset monitor.
5	5	RSTIN	Reset Input. High-impedance input to the adjustable reset comparator. Connect RSTIN to the center point of an external resistor divider to set the threshold of the externally monitored voltage.
6			Manual Reset Input. Internal 50kQ pullup to VCc. Pull MR low to immediately assert MROUT. MR does not affect RESET output.
	6	MR	Manual Reset Input. Internal 50kQ pullup to VCC. Pull MR low to immediately assert MROUT. RESET changes from high to low after MR input is held low for the 3.36s (typ) setup period.

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