suppliers of MXSMCJLCE54TR and PDF data of MXSMCJLCE54TR

MAIN MEMORY PAGE TO BUFFER COMPARE:A page of data in main memory can be compared to the data in buffer 1 0r buffer 2. An 8-bit opcode, 60H for buffer l and 61H for buffer 2, is followed by 24 address bits consisting of the five reserved bits, 10 address bits (PA9-PAO) which specify the page in the main memory that is to be compared to the buffer, and nine don't care bits. The loading of the opcode and the address bits is the same as described previously. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don't care bits from the Sl pin. On the low to high transition of the CS pin, the 264 bytes in the selected main memory page will be com- pared with the 264 bytes in buffer l or buffer 2. During this time (tXFR), the status register will indicate that the part is busy. On completion of the compare operation, bit 6 0f the status register is updated with the result of the compare.