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MXSMCJLCE48A Datasheet

POWER SUPPLY GH LEVEL LOW LEVEL
Dual Supply = +5V 1.5V 0.5V
Single Supply = 10V 6.5V 5.5V
Single Supply = 5V 1.5V O5V
Single Supply = 3.3V 1.2V 0.5V


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If another supply is provided at VINB, the LTC4413 will likewise regulate the gate voltage on PB to maintain the output voltage VOUTB just below the input voltage VINB. If this alte mate supply, VINB, exceeds the voltage at VINA,the LTC4413 will select this input voltage as the internal supply (VDD). This second ideal diode operates indepen- dently of the first ideal diode function.
MXSMCJLCE48A on stock
4. Designed and packaged for board placement with automatic equipment Headers are designed with a pick up area to accommodate the pick-and -place nozzles of automatic mounting machines. (Patents pending) Receptacles are designed to be mounted on top the board, and automatic mounting is possibble on the specified board.

Limits
Symbol Parameter Test conditions Min Typ Max Unit
V (BR) DSS Drain-source breakdown voltage ID = ImA, VGs = OV 800 v
V (BR) GSS Gate-source breakdown voltage IGS = +100ffA, VDS = OV ±30 v
IGSS Gate-source leakage current VGS = +25V, VDS = OV ±10
IDSS Drain-source leakage current VDS = 800V, VGS = OV 1 mA
VGS (th) Gate-source threshold voltage ID = 1ffiA, VDS = 10V 2 3 4 v
rDS (ON) Drain-source on-state resistance ID = 3A, VGS = 10V 1 26 1 64
VDS (ON) Drain-source on-state voltage ID = 3A, VGS = 10V 3 78 4 92 v
yfs Forward transfer admittance ID = 3A, VDS = 10V 4 2 7.0 S
Ciss Input capacitance 1380 pF
Coss Output capacitance VDS=25V,VGS=Oy f=1MHz 140 pF
Crss Reverse transfer capacitance 28 pF
td (on) Turn-on delay time 25 ns
tr Rise time VDD = 200y ID = 3A, VGS = 10V, 28 ns
td (off) Turn-off delay time RGEN = RGS = sol 185 ns
tf Fall time 46 ns
VSD Source-drain voltage Is = 3A, VGS = OV 1.0 1 5 v
Rth (ch-c) rhermal resistance Channel to case 0 83 IC/W