| When the RF input (PIN) is off, the gate voltage (VGG2) is set t0 0.4 V | | The formula*i where VGG2=f (IDD: VGG2=0.4 V) | | The output power (POUT) |
| and IDD iS read. | | is used to set VGG2. | | is adjusted t0 21.0 dBm. |
| | | | |
NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 3. Measured in open loop mode PLL_EN = 0. 4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies 5. tPD measured at device inputs at 0.5VDD, Q output at 80MHz.
