| Parameter | Min Max Unit | Comments |
| MASTER CLOCK AND RESET tMH MCLK High tML MCLK Low tPDR PD/RST Low | 15 ns 15 ns 20 ns | |
| SPI PORT tCCH CCLK High tCCL CCLK Low tCCP CCLK Period tCDS CDATA Setup tCDH CDATA Hold tcLs CLATCH Setup tCLH CLATCH Hold tCOE COUT Enable tCOD COUT Delay tCOT5 COUT Three-State | 40 ns 40 ns 80 ns 10 ns 10 ns 10 ns 10 ns 15 ns 20 ns 25 ns | To CCLK rising edge From CCLK rising edge To CCLK rising edge From CCLK rising edge From CLATCH falling edge From CCLK falling edge From CLATCH rising edge |
| DAC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Slave) tDBH DBCLK High tDBL DBCLK Low fDB DBCLK Frequency tDLS DLRCLK Setup tDLH DLRCLK Hold tDDS DSDATA Setup tDDH DSDATA Hold Packed 128/256 Modes (Slave) tDBH DBCLK High tDBL DBCLK Low fDB DBCLK Frequency tDLS DLRCLK Setup tDLH DLRCLK Hold tDDS DSDATA Setup tDDH DSDATA Hold | 60 ns 60 ns 64 x fs 10 ns 10 ns 10 ns 10 ns 15 ns 15 ns 256 x fs 10 ns 10 ns 10 ns 10 ns | To DBCLK rising edge From DBCLK rising edge To DBCLK rising edge From DBCLK rising edge To DBCLK rising edge From DBCLK rising edge To DBCLK rising edge From DBCLK rising edge |
| ADC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Master) tABD ABCLK Delay tALD ALRCLK Delay tABDD ASDATA Delay Normal Mode (Slave) tABH ABCLK High tABL ABCLK Low fAB ABCLK Frequency tALS ALRCLK Setup tALH ALRCLK Hold tABDD ASDATA Delay Packed 128/256 Mode (Master) tPABD ABCLK Delay tPALD LRCLK Delay tPABDD ASDATA Delay | 25 ns 5 ns 10 ns 60 ns 60 ns 64 x fs 5 ns 15 ns 15 ns 40 ns 5 ns 10 ns | From MCLK rising edge From ABCLK falling edge From ABCLK falling edge To ABCLK rising edge From ABCLK rising edge From ABCLK falling edge From MCLK rising edge From ABCLK falling edge From ABCLK falling edge |
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