| | TEST' | 2 | DESCRIPTIONi | -125 | -100 | |
| PARAMETER | COND | MIN | MAX | MIN | MAX | UNITS |
| tpdl | A | 1 | Data Propagation Delay, 4PT Bypass, ORP Bypass | | 7.5 | | 10.0 | ns |
| tpd2 | A | 2 | Data Propagation Delay, Worst Case Path | | 10.0 | | 12.5 | ns |
| fmax (lnt.) | A | 3 | Clock Frequency with Internal Feedback 3 | 125 | | 100 | | MHz |
| fmax (Ext.) | | 4 | Clock Frequency with External Feedback tsu2~t~o ) | 91.0 | | 71.0 | | MHz |
| fmax (Tog.) | | 5 | Clock Frequency, Max. Toggle ( tri t ) | 167 | | 125 | | MHz |
| tsul | | 6 | GLB Reg. Setup Time before Clock,4 PT Bypass | 5.0 | | 7.0 | | ns |
| tcol | A | 7 | GLB Reg. Clock to Output Delay, ORP Bypass | | 5.0 | | 6.0 | ns |
| thl | | 8 | GLB Reg. Hold Time after Clock, 4 PT Bypass | 0.0 | | 0.0 | | ns |
| tsu2 | | 9 | GLB Reg. Setup Time before Clock | 6.0 | | 8.0 | | ns |
| tc02 | | 10 | GLB Reg. Clock to Output Delay | | 6.0 | | 7.0 | ns |
| th2 | | 1 1 | GLB Reg. Hold Time after Clock | 0.0 | | 0.0 | | ns |
| trl | A | 12 | Ext. Reset Pin to Output Delay | | 10.0 | | 13.5 | ns |
| trwl | | 13 | Ext. Reset Pulse Duration | 5.0 | | 6.5 | | ns |
| tptoeen | B | 14 | Input to Output Enable | | 12.0 | | 15.0 | ns |
| tptoedis | c | 15 | Input to Output Disable | | 12.0 | | 15.0 | ns |
| tgoeen | B | 16 | Global OE Output Enable | | 7.0 | | 9.0 | ns |
| tgoedis | c | 17 | Global OE Output Disable | | 7.0 | | 9.0 | ns |
| twh | | 18 | External Synchronous Clock Pulse Duration, High | 3.0 | | 4.0 | | ns |
| twl | | 19 | External Synchronous Clock Pulse Duration, Low | 3.0 | | 4.0 | | ns |
| tsu3 | | 20 | I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) | 3.0 | | 3.5 | | ns |
| th3 | | 21 | I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) | 0.0 | | 0.0 | | ns |
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