| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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MI-P7W-MYX Datasheet -.-L-H h--N (50 80 +0 38) NOTES: All dimensions are in inches (millimeters). Product is marked with specific model ordered, date code and job code. GRID: O.100 inches (2.54 millimeters) PIN PLACEMENT TOLERANCE: +0.015 MI-P7W-MYX Price
MI-P7W-MYX on stock
On the receive path, the AT78C5090 performs the serial-to-parallel conversion, using a high bandwidth clock and data recovery (CDR) block. The recovered data is then passed through a comma alignment block and an optional 8B/10B decode block before being passed to the phyCtrl layer via a parallel interface. This interface is syn- chronous to the recovered clock. |
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