Based on ARM920T core, the S3C2800 is developed using 0.18 um CMOS standard cells and a memory compiler. Its simple, elegant, and fully static low-power design is particularly suitable for both cost-sensitive and power-sensitive applications. The 32-bit ARM920T RISC processor core (220Mips @200MHz), designed by Advanced RISC Machines, Ltd., provides architectural enhancements such as the Thumb de-compressor, a 32- bit hardware multiplier, and an on-chip ICE debug support. Also, the S3C2800 features the Harvard BUS architecture for efficient data/instruction transfers.
| PIN CONNECTIONS Single Dual 1, 24 +Vin + Vin 2, 23 No Pin -Vout 3, 22 No Pin Common |
| 10, 15 - Vout Common |
| 11, 14 + Vout + Vout |
| 12, 13 - Vin - Vin |
6 Trim Com Com (Aux) Com 7 Trim Up -Vout -Aux +5V 8 +Vout Trim +Vout(Primary) Trim 9 -Vout NC Com(Primary) NC 10 No Pin NC Trim NC NC = No Connection
