| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| MAX4914BLA | MAX | UDFN-8 | 2008+ | 10000 |
|
MAX4914BLA Datasheet
MAX4914BLA on stock *Features 1) 40-bit shift register and 40-bit latch enable seria input - parallel output. 2) Shift register can be divided into tw0 20-bit sections. 3) Power supply voltage: 3.5 t0 6V. 4) LCD drive voltage: 3 t0 6V. The output matching network must provide the optimum load resistance to the RF110 0utputs as well as convert the differential signals to a single-ended signal into a so I load. The output matching network should present a differential impedance of approximately 59-j10 I to the output of the RF110, with a 1800 phase difference between the two branches VDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Operating Temperature Range Commercial (B Version) Storage Temperature Range |
