* Double-buffer mode transmitter/receiver ~ Dual transmit/receive of communication is practicable for all 4 channels. * Setting of transfer rate at each channel for both hardware and software is practicable. When input clock is 14.745 6 MHz, the following rates are applicable. 614.4 KHz, 307.2 KHz, 153.6 KHz, 76.8 KHz, 38.4 KHz, 19.2 KHz, 9.6 KHz and 4.8 KHz * Freedom of combination oflogical address with physical address for 4 channels. ~ Data length 8 bit, stop bit l bit fixed. ~ Overrun and framing error are detectable. * Error start bit is detectable. * Direct connection t0 8 bit bidirectional data bus and data bus is practicable. * 4 bit address input. *Hardware interrupt signal of TXRDY and RXRDY that can be masked. ~ Connection to high speed CPU is practicable. ~ SV single voltage supply. ~ 60 pin flat package.
LC35W256ET-10WTSSOP on stock| Symbol | Parameter | Min | Max | Units |
| fSCK | Clock Frequency | 0 | 1 | MHz |
| tDIS | Output Disable Time | | 500 | ns |
| tv | Output Valid from Clock LOW | | 400 | ns |
| tHO | Output Hold Time | 0 | | ns |
| tR0(3) | Output Rise Time | | 300 | ns |
| tF0(3) | Output Fall Time | | 300 | ns |
| tLZ | HOLD HIGH to Output in Low Z | 1 00 | | ns |
| tHZ | HOLD LOW to Output in High Z | 1 00 | | ns |
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| | | | | Vcs= -2.5V | |
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| | | | | | | 3 V |
| | __- | | | ____ | | __-3.5V |
| | | | | | | - 4.5 V' |
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