IXTH11N80A Datasheet -32 Byte Small Sector Program Mode Low Power CMOS -<1 Standby Current -<5mA Active Current 1.8V - 3.6V or 5V "Univolt" Read and Program Power Supply Versions Block Lock Protection -Protect l/4, 1/2, or all of E2PROM Array Built-in Inadvertent Program Protection - Power-Up/Power-Down protection circuitry -Program Enable Latch -Program Protect Pin Self-Timed Program Cycle -5ms Program Cycle Time (Typical) High Reliability -Endurance: 100,000 cycles per byte -Data Retention: 100 Years IXTH11N80A Price 8 9 8 8 a r - r n 3 w ( d d ) q o O a o N v i o v d v o m c u n o a o i o a n o o IXTH11N80A on stock| | MEMORY SIZE 4kx8 | MEMORY SIZE 8kx8 | MEMORY SIZE 16kx8 | MEMORY SIZE 32kx8 | TEMPERATURE RANGE YC AND PACKAGE | VOLTAGE RANGE | FREQ. (MHz) | DWG | | FLASH | P89C51UBAA | P89C52UBA A | P89C54UBA A | P89C58UBA A | 0 to +70, Plastic Leaded Chip Carrier | 5V | O t0 33 | SOT187-2 | | FLASH | P89C51UBP N | P89C52UBP N | P89C54UBP N | P89C58UBP N | 0 to +70, Plastic Dual In-line Package | 5V | O t0 33 | SOT129-1 | | FLASH | P89C51UBB B | P89C52UBB B | P89C54UBB B | P89C58UBB B | 0 to +70, Plastic Quad Flat Pack | 5V | O t0 33 | QFP442 | | FLASH | P89C51UFAA | P89C52UFA A | P89C54UFA A | P89C58UFA Ai | -40 to +85, Plastic Leaded Chip Carrier | 5V | O t0 33 | SOT187-2 | | FLASH | P89C51UFP N | P89C52UFP N | P89C54UFP N | P89C58UFP Ni | -40 to +85, Plastic Dual In-line Package | 5V | O t0 33 | SOT129-1 | | FLASH | P89C51UFB B | P89C52UFB B | P89C54UFB B | P89C58UFB Bi | -40 to +85, Plastic Quad Flat Pack | 5V | O t0 33 | QFP442 | | | | | | | | | |
| Product Vz nom. Vz min. Vz max. Iz max. Zz max. VR test IR max. Tcvz ZK max. IR max(2) min. max. | | BZX55C2V4 2.4 2.28 2.56 155 85 1.0 50 -0.08 -0.06 600 100 BZX55C2V7 2.7 2.5 2.9 135 85 1.0 10 -0.08 -0.06 600 50 BZX55C3V0 3.0 2.8 3.2 125 85 1.0 4.0 -0.08 -0.06 600 40 BZX55C3V3 3.3 3.1 3.5 115 85 1.0 2.0 -0.08 -0.05 600 40 BZX55C3V6 3.6 3.4 3.8 105 85 1.0 2.0 -0.08 -0.04 600 40 BZX55C3V9 3.9 3.7 4.1 95 85 1.0 2.0 -0.07 -0.03 600 40 BZX55C4V3 4.3 4.0 4.6 90 75 1.0 1.0 -0.04 -0.01 600 20 BZX55C4V7 4.7 4.4 5.0 85 60 1.0 0.5 -0.03 +0.01 600 10 BZX55C5V1 5.1 4.8 5.4 80 35 1.0 0.1 -0.02 +0.05 550 2.0 BZX55C5V6 5.6 5.2 6.0 70 25 1.0 0.1 -0.01 +0.06 450 2.0 BZX55C6V2 6.2 5.8 6.6 64 10 2.0 0.1 0 +0.07 200 2.0 BZX55C6V8 6.8 6.4 7.2 58 8.0 3.0 0.1 +0.01 +0.08 150 2.0 BZX55C7V5 7.5 7.0 7.9 53 7.0 5.0 0.1 +0.01 +0.09 50 2.0 BZX55C8V2 8.2 7.7 8.7 47 7.0 6.2 0.1 +0.01 +0.09 50 2.0 BZX55C9V1 9.1 8.5 9.6 43 10 6.8 0.1 +0.02 +0.10 50 2.0 BZX55C10 10 9.4 10.6 40 15 7.5 0.1 +0.03 +0.11 70 2.0 BZX55C11 11 10.4 11.6 36 20 8.2 0.1 +0.03 +0.11 70 2.0 BZX55C12 12 11.4 12.7 32 20 9.1 0.1 +0.03 +0.11 90 2.0 BZX55C13 13 12.4 14.1 29 26 10 0.1 +0.03 +0.11 110 2.0 BZX55C15 15 13.8 15.6 27 30 11 0.1 +0.03 +0.11 110 2.0 BZX55C16 16 15.3 17.1 24 40 12 0.1 +0.03 +0.11 170 2.0 BZX55C18 18 16.8 19.1 21 50 13 0.1 +0.03 +0.11 170 2.0 BZX55C20 20 18.8 21.2 20 55 15 0.1 +0.03 +0.11 220 2.0 BZX55C22 22 20.8 23.3 18 55 16 0.1 +0.03 +0.11 220 2.0 BZX55C24 24 22.8 25.6 16 80 18 0.1 +0.04 +0.12 220 2.0 BZX55C27 27 25.1 28.9 14 80 20 0.1 +0.04 +0.12 220 2.0 BZX55C30 30 28 32 13 80 22 0.1 +0.04 +0.12 220 2.0 BZX55C33 33 31 35 12 80 24 0.1 +0.04 +0.12 220 2.0 BZX55C36 36 34 38 11 80 27 0.1 +0.04 +0.12 220 2.0 BZX55C39 39 37 41 10 90 30 0.1 +0.04 +0.12 500 5.0 BZX55C43 43 40 46 9.2 90 33 0.1 +0.04 +0.12 600 5.0 BZX55C47 47 44 50 8.5 110 36 0.1 +0.04 +0.12 700 5.0 BZX55C51 51 48 54 7.8 125 39 0.1 +0.04 +0.12 700 10 BZX55C56 56 52 60 7.0 135 43 0.1 +0.04 +0.12 1000 10 BZX55C62 62 58 66 6.4 150 47 0.1 +0.04 +0.12 1000 10 BZX55C68 68 64 72 5.9 200 51 0.1 +0.04 +0.12 1000 10 BZX55C75 75 70 80 5.3 250 56 0.1 +0.04 +0.12 1500 10 |
| Pin Name | Pin Type | Pin Description | Circuit Number | SDIP Pin Number | Share Pins | | PO.O-P0.7 | I/O | I/O port with nibble-programmable pins; Input or push-pull, open-drain output and software assignable pull-ups; also configurable as external interface address lines A8-A15. | E | 1-7, 64 | A8-A15 | | P1.O-P1.7 | 1/0 | Same general characteristics as port 0; also configurable as external interface address/data lines ADO-AD7. | E | 56-63 | ADO-AD7 | | P2.O-P2.3 P2.4-P2.7 | I/O | I/O port with bit-programmable pins; Input or push-pull output. Lower nibble pins 0-3 are configurable for external interface signals; upper nibble pins 4-7 are bit- programmable for external interrupts INTO- INT3. P2.4 can also be used for external WAIT input. | D-1 (lower nibble); D-1 (upper nibble; with noise filter) | 40-47 | AS, DS, DM, R/w INTO-INT3, WAIT | | P3.O-P3.7 | I/O | I/O port with bit-programmable pins; Input or push-pull output. Alternate functions include software-selectable UART transmit and receive on pins 3.7 and 3.6, timer B and timer A outputs at pins 3.5 and 3.4, and timer D and C clock inputs at pins 3.1 and 3.0. | D-1 | 24- 31 | TCCK, TDCK, TA, TB, TxD, RxD | | P4.O-P4.7 | I/O | I/O port with bit-programmable pins; Input or push-pull output; software-assignable pull-ups. Alternate functions include external interrupt inputs INT4-INT11 (with interrupt enable and pending control) and timer C and D gate input at P4.0 and P4.1. | D (with noise filte r) | 8-15 | INT4- INT11, TCG, TDG | | P5.O-P5.7 | I/O | I/O port with nibble-programmable pins; Input or push-pull, open-drain output; software-assignable pull-ups. | E | 21, 22, 50-55 | | | P6.O-P6.7 | O | Output port with nibble-programmable pins; push-pull, open-drain output; software- assignable pull-ups. | E-8 | 32-39 | | | RxD | I/O | Bi-directional serial data input pin | | 24 | P3.7 | | TxD | I/O | Serial data output pin | | 25 | P3.6 | | TATB | I/O | Timer A and B output pins | 4 | 27, 26 | P3.4P3.5 | | TCCKDCK | I/O | Timer C and D external clock input pins | D-1 | 30, 31 | P3.0P3.1 | | INTO-INT3 | 1/0 | External interrupts. 1/0 pin 2.4 (share pin with INTO) is also configurable as a WAIT signal input pin for the external interface. | D-1 (with noise filte r) | 40-43 | P2.4-P2.7 | | | | | | |
|
