| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| IP-25L-CW | IP | MODULE | IN STOCK | 10 |
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| IP-25L-CW | IP | 432 |
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| IP-25L-CW | IP | 10 |
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| IP-25L-CW | IP | 432 |
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| IP-25L-CW | 300 | IP | 02+ |
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| IP-25L-CW | IP | 432 |
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IP-25L-CW Datasheet
IP-25L-CW Price - 2 memory banks, non-interleaved, 572 MB total - 32-bit wide data path - Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips - SODIMMsupport - Stays on page between transfers - Automatic refresh generation + Peripheral Device Controller - 26-bit address bus become low impedance when the Frame Sync signal FST is high or when the 8 bit data word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes low while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section. |
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