GE7500PL-SL64H Datasheet| PARAMETER | SYMBOL | CONDITIONS/DESCRIPTION | MIN | TYP | MAX | UNITS | | Overall | | Skew, Output to Output * | tsk(01 | Measured on the rising edge at l.65V; CL = 15pF | | | 150 | ps | | Skew, Tracking * | | Measured using a -0.5% 31.5kHz spread spectrum reference clock at 133.33MHz | | | 150 | ps | | Static Phase Error* | | From rising edge on CLK to rising edge on FBIN | | -120 | | ps | | Clock Stabilization Time * | | Time required for the PLL to achieve phase lock | | | 3 | ms | | Loop Bandwidth * | | For calculation of Tracking Skew | | | 1.2 | MHz | | Phase Angle * | | For calculation of Tracking Skew | | | -0.031 | Y | | Clock Outputs (1Y0:4, 2Y0:3, FBOUT) | | Duty Cycle+ | d | Ratio of high pulse width to one clock period, measured at l.65V | 45 | | 55 | % | | Jitter, Cycle-Cycle * | tj(CC) | Adjacent cycles at l.65V | -75 | | +75 | ps | | Jitter, Period (peak-peak) * | tj(EP) | From rising edge to next rising edge at l.65V | | | | | | Rise Time+ | tr | Vo = 0.4V t0 2.OV; CL = 15pF | | 1 2 | | ns | | Fall Time+ | tf | Vo = 2.OV t0 0.4V; CL = 15pF | | 1 4 | | ns | | Enable Delay * | tDLH | via lG or 2G | 1 | | 10 | ns | | Disable Delay * | tDHL | via lG or 2G | 1 | | 10 | ns | | | | | | | |
GE7500PL-SL64H Price| I\_/I - - - - . I\_/li 'I\-/ j tAC(MAX) | _ - _ | __} | -/l= . \_1-/ | | ________ \-l-/ | | 4- LDOSH | 1tDQSH7 | | | -111y | | : tACcMlrl) | | __h ____________________________ | 7 | | \l__/. | | LOOSH | LOOSH | | 111y | | | | | | | | | | |
GE7500PL-SL64H on stock| | UF600 | UF601 | UF602 | UF604 | UF606 | UF608 | UNITS | | Peak Reverse Voltaqe, Pepetitive ; VPM | 50 | 1 00 | 200 | 400 | 600 | 800 | V | | Maximum RMS Voltaqe | 35 | 70 | 140 | 280 | 420 | 560 | V | | DC Blockinq Voltaqe; VR | 50 | 1 00 | 200 | 400 | 600 | 800 | V | | Average Forward Current, lo @TA=55 CJ3.8" lead lenqth, 60Hz, resistive or inductive load | 6O | A | | Peak Forward Surge Current IFM (surge) 8.3msec. single half sine-wave superimposed on rated load (JEDEC method) | 300 | A | | Maximum Forward Voltage VF @6.OA, 25 CJ | 1.00 | 1.10 | 1.70 | V | | Maximum Reverse Current, @ Rated Tj95 CJ Reverse Voltage TJ=100 CJ | 10.0 1 000 | gA gA | | Typical Junction capacitance (Note l) CJ | 300 | pF | | Typical Junction Resistance (Note 2) R ~KJA | 1 0O | CW | | Reverse Recovery Time IF=.5A, lp=lA, lrr=.25A | 50 | 50 | 50 | 50 | 75 | ns | | Operating and Storage Temperature Range | -55 TO +150 | CJ | | | | | | | | |
Reliability and performance are designed in. The bifilar wound, wirebonded transformer simultaneously provides lower output ripple than competing designs, and a higher performance/cost ratio. The soft-start oscillator/driver design assures full operation of the
|
