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A new audio input frame begins with a low to high transition of SYNC as shown in Figure 11. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, WM9701A samples the assertion of SYNC. This falling edge marks the time when both sides of AC- link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller transitions SDATA_IN into the first bit position of slot 0 (valid frame bit). Each new bit position is presented to AC-Iink on a rising edge of BIT_CLK, and subsequently sampled by the AC'97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned.
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