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ISample tested at +25IC to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% t0 90% of +5 V) and timed from a voltage level of +1.6 V. 2The SCLK maximum frequency is 16 MHz. Care must be taken when interfacing to account for the data access time, t4, and the setup time required for the user's processor. These two times will determine the maximum SCLK frequency with which the user's system can operate. See Serial Interface section for more information 3Measured with the load circuit of Figure l and defined as the time required for an output to cross 0.8 V or 2.0 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure l. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t6, quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of extemal bus loading capacitances. Specifications subject to change without notice.