| DO-D7 CSN R/WN A1-A4 RESETN DTACKN INTRN IACKN | 28, 18, 27, 19, 26, 20, 25, 21 39 9 2, 4, 6, 7 38 10 24 41 | 25, 16, 24, 17, 23, 18, 22,19 35 8 1, 3, 5, 6 34 9 21 37 | 1/0 l I I 1 0 0 I | Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART and the CPU. DO is the least significant bit. Chip Select: Active-LOW input signal. When LOW, data transfers between the CPU and the DUART are enabled on DO-D7 as controlled by the R/WN, RDN and Al-A4 inputs. When HIGH, places the DO-D7 lines in the 3-State condition. Read/Write: A HIGH input indicates a read cycle and a LOW input indicates a write cycle, when a cycle is initiated by assertion of the CSN input. Address Inputs: Select the DUART internal registers and ports for read/write operations. Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex OF, puts OPO-OP7 in the HIGH state, stops the counter/timer, and puts Channel A and B in the inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Clears Test modes, sets MR pointer to MRl. Data Transfer Acknowledge: Three-state active LOW output asserted in write, read, or interrupt cycles to indicate proper transfer of data between the CPU and the DUART. Interrupt Request: Active-LOW, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. Interrupt Acknowledge: Active-LOW input indicating an interrupt acknowledge cycle. In response, the DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending. |
