| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| CD54LS02F3A | 3800 | 2003 | HAR TI |
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| CD54LS02F3A | HAR | DIP | 02+03+ | 200 |
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| CD54LS02F3A | HAR/TI | 04+ | CDIP |
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| CD54LS02F3A | 08+ | ORIGINAL | 1000 | CDIP |
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CD54LS02F3A Datasheet The 16 bits following the data field are the frame check sequence bits. The generator polynomial is: G(x)=x16+x12+x5+1 The transmitter calculates the FCS on all bits of the data field and transmits after the data field and before the end flag. The receiver performs a similar computation on all bits of the received data and FCS fields and the result is compared with FOB8Hex. If it matches, the received data is assumed error free. The error status of the received packet is indicated by D7 and D6 bits in the FIFO Status Register. CD54LS02F3A Price 1. Minimum voltage is -0.6V DC which may under- shoot to -2.OV for pulses ofless than 20 ns. Max- imum output pin voltage is Vcc + 0.75V DC which may overshoot to +7.OV for pulses of less than 20 ns. CD54LS02F3A on stock
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