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C1206JRNPO0BN120 1206-12P 100V YAGEO        28000 


C1206JRNPO0BN120 1206-12P 100V YAGEO         

C1206JRNPO0BN120 1206-12P 100V Datasheet

Symbol Parameter Test Conditions Min Typ. Max Unit
% Output Voltage 17.1 18 18.9 v
Va Output Voltage lo = 1 A Vi = 20.5 V 17 18 19 v
Vo Line Regulation Vi = 20.5 t0 30 V Vi = 22 t0 28 V 360 180 mV mV
o Load Regulation lo = 20 mA t0 1.5 A lo = 2A 200 360 mV
Id Quiescent Current 8 mA
Cld Quiescent Current Change lo = 20 mA t0 1A O5 mA
gd Quiescent Current Change lo = 20 mA Vi = 20.5 t0 30 V 1 mA
V 07- Output Voltage Drift lo = 5 mA Tj = 0 t0 70 0C 1 mV/oC
eN Output Noise Voltage B = 10Hz t0 100KHz 110
SVR Supply Voltage Rejection f= 120 Hz 43 dB
Vi Operating Input Voltage lo1.5 A 21 v
R Output Resistance f= 1KHz 22 ml
lsc Short Circuit Current Vi= 27 V 500 mA
lscp Short Circuit Peack Current 3 A


C1206JRNPO0BN120 1206-12P 100V Price

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C1206JRNPO0BN120 1206-12P 100V on stock
The remaining 8K of data memory is located off-chip. This external data memory is divided into three zones, each associ- ated with its own wait-state generator. This allows slower pe- ripherals to be memory-mapped into data memory for which wait states are specified. By mapping peripherals into different zones, you can accommodate peripherals with different wait- state requirements. All zones default t0 7 wait states after
CAUTION: These devices are sensitive to electrostatic discharge; follow proper lC Handling Procedures. 1-888-INTERSIL or 321-724-7143 I Intersil and Design is a trademark of Intersil Corporation. I Copyright Intersil Corporation 2000

Pin No. Symbol Description
1 - 5, 18 - 22, 24 - 27, 42 - 44 AO - A16 Address Inputs
6 CE Chip Enable Input
7 - 10, 13 - 16, 29 - 32, 35 - 38 l/0i - l/016 Data Inputs/Outputs
17 WE Write Enable Input
39 LB Lower Byte Enable lriput (l/0i to l/08)
40 HB Higher Byte Enable Input (l/09 to l/016)
41 OE Output Enable Input
11, 33 VCC Power
12, 34 GND Ground
23, 28 NC No Connection