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Part Numbert	Mfg	Packt	D/C	Descriptiont	Qty	Company/Contact
ATA6841N-PLSW	ATMEL		2009ROHS		6400	All Element Technology Co.,Ltd Contact:lisa Tel:86-755-82565926 Fax:86-755-82565338 Email: lisa@allelement.net
ATA6841N-PLSW	ATMEL	QFN-48	2009ROHS		6400	Sun Asia component Contact:luisa Tel:86-755-83290093 Fax: Email: szhuadian@126.com

ATA6841N-PLSW Datasheet

SYMBOL	PIN NUMBER	TYPE	DESCRIPTION
CLOCK AND RESET SIGNALS
CLR#	32	l	reset signal, active low
XIN	8	l	Crystal oscillator input pin. When USE_NCO pin is high a third overtone XTAL should be connected between the XIN and XOUT pins. When USE_NCO pin is low a VCXO should be connected between XIN and via a RC filter to the CTRL_VCXO output.
XOUT	9	O	Crystal oscillator output pin.
SACLK	25	O (5V)	Sampling frequency output. This output clock can be fed to an external (10-bit) ADC as sampling clock. SACLK= XIN/2
USE NCO	33	l	When low the chip is in VCXO mode else in NCO mode
CTRL VCXO	26	O (5V)	If not in NCO mode, control of an external sampling VCXO (after low- pass filtering)
CLK X1	1 81	O (5V)	Internal SACLK equivalent monitoring output.
CLK X2	1 80	O (5V)	Internal SACLK* 2 equivalent monitoring output.

ATA6841N-PLSW Price

The integrator capacitor CINT (see Figure l) affects the magnitude of the integrator voltage waveform. Its absolute accuracy is not critical since it does not affect the transfer function. This allows a wide range of capacitance to produce excellent results. Figure 4 facilitates choosing an appropriate
ATA6841N-PLSW on stock

Parameter	Sym	Ratings	Unit
Power Supply Voltage	VDD	6.0	V
Input Voltage Range	V,.,	-0.3 VDD + 0.3	V
Operating Temperature	TOPR	050	C
Storage Temperate	Tsro	-55125	C
Power Dissipation	PD	500	mw

Parameter	Rating	Unit
Supply Voltage Power Control Voltage (VREG) DC Supply Current Input RF Power Operating Ambient Temperature Storage Temperature Moisture sensitivity	-0.5 to +6.0 -0.5 t0 3.5 600 +10 -40 to +85 -40 to +150 JEDEC Level 3	VDC V mA dBm oC oC

respectively, and FO~ is used only for the watchdog timer operation. When this bit is a ONE, the Protocol Controller is in the Internal Timing Mode. The transmit and receive sections are enabled by the internally generated timings derived from the inputs CKi and FOi. The FOi input defines the beginning of a frame (Figure 24) and the transmitter and receiver sections are enabled in the timeslots as determined

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