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Independent power down control for all of the major blocks within the chip is provided via three bits in the control register (SYNC_PWR_DN, STH_PWR_DN and PD_PWR_DN) to manage power consumption. In addi- tion, two pins (SLEEP and IDLE/SERVO) are available to control power management. The sleep mode pin (SLEEP) powers down all circuitry on the chip including the control register. In this mode the maximum power supply current is 2 mA; the control register data must be reentered when exiting this mode. The idle/servo mode pin (IDLE/SERVO) toggles the device between the idle and servo modes. In the idle mode, only the control register and pulse detector bias- ing circuitry necessary for a quick recovery are active. In the servo mode, the pulse detector portions needed for servo detection are active as well as the control register. Less than 15 lLS iS required for the pulse detector to recover from the idle condition. The control register data is not lost when this pin is toggled. The pin can be rapidly toggled 15 p,S) to achieve average power consumption savings and will keep the read/write head on track. Seventeen power and ground pins are provided to isolate major functional blocks and allow for independent supply voltage filtering, thus en- hancing noise immunity. (Continued)