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NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CEl and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CEl or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5.lfthe CEl low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. Dou r is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CEl is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. Tcw iS measured from the later of CEl going low or CE2 going high to the end of write.