| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| AD8402AR | SOP | NA | 580 |
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| AD8402AR | 13 | AD | 2007 |
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| AD8402AR | AD | 1,455 |
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| AD8402AR | AD | CS5 | 09+ | 优势库存,欢迎来电! | 4921 |
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| AD8402AR | AD | SOP14 | 500 |
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| AD8402AR | AD | SMD | 2006 | original in stock | 3500 |
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| AD8402AR | AD | 04+ | 2 |
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| AD8402AR | N/A | SOP | NA | 588 |
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| AD8402AR | AD | CS5 | 09+ | 119 |
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| AD8402AR | ADI | SOP14 | 08年无铅 | 原装现货,品质为先! | 340 |
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| AD8402AR | AD | 14 | SOIC8 | 2007 |
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| AD8402AR | AD | SOP-16 | 14 |
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| AD8402AR | AD | 700 |
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| AD8402AR | 580 |
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| AD8402AR | AD | SOIC8 | 08+ | 750 |
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| AD8402AR | sop | 1489 |
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| AD8402AR | AD | 700 |
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| AD8402AR | A48 | NA | 580 |
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| AD8402AR | AD | SOP14 | N/A | STOCK | 100 |
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| AD8402AR | AD | SOP-14 | 2007 | NEW AND BLANK | 140 |
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| AD8402AR | AD | SMD | 60 |
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| AD8402AR | AD | SMD | 2006 | ORIGINAL | 3500 |
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| AD8402AR | AD | SOP14 | 06+ | 4500 |
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| AD8402AR | AD | 2007 | stock | 14 |
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| AD8402AR | AD | SOP | N/A | 5 |
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| AD8402AR | AD | SOP | N/A | 5 |
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| AD8402AR | AD | SMD | 08/09+ | 48 |
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| AD8402AR | AD | 14 | SOIC8 | 2007 |
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| AD8402AR | AD | 08+ | stock on hand | 5000 |
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| AD8402AR | AD | 05+ | email/MSN: eteasia@g | 183 |
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| AD8402AR | AD | SMD | 03+ | 28 |
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| AD8402AR | AD | 1,455 |
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| AD8402AR | AD | SOP14 | 15 |
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| AD8402AR | AD | SMD | 08+ | Stock | 3520 |
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| AD8402AR |
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| AD8402AR | SOP | 580 |
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| AD8402AR | 724 | ADI | SOP |
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| AD8402AR | AD | SOP-16 | 14 |
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| AD8402AR | ADI | SOP | 724 |
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| AD8402AR | N/A | 08+ ROHS | Original 100% mik | 580 |
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| AD8402AR | Original pac | 2500 | AD |
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| AD8402AR | AD | new | 2007 | SOP |
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| AD8402AR | 08+ | ORIGINAL | 1255 | SOP-14 |
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| AD8402AR | 14 | AD | 2007 |
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| AD8402AR | AD | 04+ | 4 |
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| AD8402AR | 05+ | 140 |
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| AD8402AR | AD | SOP | 900 |
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| AD8402AR | AD | QFP-160 | 00+ |
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| AD8402AR | 580 |
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AD8402AR Datasheet PROTECTING THE DEVICE AGAIST LOAD DUMP -TEST PULSE5 The device is able to withstand thetestpulse No. 5 at level lI (Vs = 46.5V) according to the ISO T/R 7637/1 without any external component. This means that all functions of the device are performed as designed after exposure to disturbanceat levelll. The VN06SP is able to withstand the test pulse No.5 at level III adding an external resistor of 150 0hm between GND pin and ground plus a filter capacitor of 1000 ~F between Vcc pin and ground (if RLOAD " 20 I ). AD8402AR Price Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Toky0 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.< il/ecg Asji~;~Lnigaapno\re) :http://wwwhashita:ch.:mmtwmT/:i8l//~gTu3lti~cid4i8dexhtm Asia (Taiwan) : http://www.hitachi.corr CD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm DRV (Pin 6): Drive Output Pin for the P-Channel MOSFET or PNP Transistor. The impedance is high at this pin, therefore,a high gain PNP pass transistor should be used. The DRV pin is internally clamped t0 8V (max) below Vcc. Byte Write For a byte write operation, the device requires the Slave Address Byte and the Word Address Bytes. This gives the master access to any one of the words in the array or CCR. (Note: Prior to writing to the CCR, the master must write a 02h, then 06h to the status regis- ter in preceding operations to enable the write opera- tion. See "Writing to the Clock/Control Registers" on page 6.) Upon receipt of each address byte, the X1240 responds with an acknowledge. After receiving both address bytes the X1240 awaits the eight bits of data. After receiving the 8 data bits, the X1240 again responds with an acknowledge. The master then ter- minates the transfer by generating a stop condition. The X1240 then begins an internal write cycle of the data to the nonvolatile memory. During the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 6. |